Implementação em VHDL da RPU de IPNOSYS

Abstract

The advances in microelectronics enabled the incorporation of multiprocessor systems into a single chip, in order to obtain performance gains through the exploration of parallelism in several levels. IPNoSys is a multicore processor based network-on-chip architecture. The programming and simulation environment of this processor allows you to execute real applications, however, some results require the description and synthesis of the hardware. In view of the above, the present work aimed to present the design, implementation and testing, in VHDL, for the RPU component of IPNoSys. The methodology used involves the adoption of a style of development oriented to tests, which prioritizes the creation of test cases before implementation. Automated tests, containing synthetic and real (sequential and/or parallel) applications, were designed to verify the correct implementation of the internal components of the RPU and the 2D matrix of RPUs. The results presented by the simulations show gains in productivity, code quality, modularity and lower error propensity.